Added sysdeps/aix directory that was missing
2002-12-30 Bastien Nocera <hadess@hadess.net> * Added sysdeps/aix directory that was missing
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Bastien Nocera
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Bastien Nocera
Bastien Nocera
parent
2661891d6a
commit
ab60fc3dd1
194
sysdeps/aix/sysinfo.c
Normal file
194
sysdeps/aix/sysinfo.c
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@@ -0,0 +1,194 @@
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/* $Id$ */
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/* Copyright (C) 1998-99 Martin Baulig
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This file is part of LibGTop 1.0.
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Contributed by Martin Baulig <martin@home-of-linux.org>, April 1998.
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LibGTop is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License,
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or (at your option) any later version.
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LibGTop is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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for more details.
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You should have received a copy of the GNU General Public License
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along with LibGTop; see the file COPYING. If not, write to the
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Free Software Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA.
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*/
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#include <sys/systemcfg.h>
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#include <config.h>
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#include <glibtop/sysinfo.h>
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static const unsigned long _glibtop_sysdeps_sysinfo =
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(1L << GLIBTOP_SYSINFO_CPUINFO);
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static glibtop_sysinfo sysinfo;
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static void add_info(glibtop_entry* entry, char* label, char* value)
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{
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g_ptr_array_add(entry->labels, g_strdup(label));
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g_hash_table_insert(entry->values, label, g_strdup(value));
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}
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static void init_sysinfo(void)
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{
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int cpu;
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char buf[64];
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memset (&sysinfo, 0, sizeof (glibtop_sysinfo));
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sysinfo.ncpu = MIN(_system_configuration.ncpus, GLIBTOP_NCPU);
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for (cpu = 0; cpu < sysinfo.ncpu ; cpu++)
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{
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/* init cpu data structure */
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sysinfo.cpuinfo[cpu].labels = g_ptr_array_new();
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sysinfo.cpuinfo[cpu].values = g_hash_table_new (NULL, NULL);
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/* add properties */
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switch(_system_configuration.architecture)
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{
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case POWER_RS:
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add_info( &sysinfo.cpuinfo[cpu]
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, "architecture"
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, "Power Classic architecture");
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break;
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case POWER_PC:
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add_info( &sysinfo.cpuinfo[cpu]
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, "architecture"
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, "Power PC architecture");
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break;
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case IA64:
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add_info( &sysinfo.cpuinfo[cpu]
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, "architecture"
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, "Intel IA64 architecture");
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break;
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default:
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add_info( &sysinfo.cpuinfo[cpu]
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, "architecture"
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, "Unknown architecture");
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break;
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}
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if ( (_system_configuration.architecture == POWER_RS) ||
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(_system_configuration.architecture == POWER_PC) )
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{
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switch(_system_configuration.implementation)
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{
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case POWER_RS1:
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add_info( &sysinfo.cpuinfo[cpu]
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, "implementation"
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, "RS1");
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break;
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case POWER_RSC:
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add_info( &sysinfo.cpuinfo[cpu]
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, "implementation"
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, "RSC");
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break;
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case POWER_RS2:
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add_info( &sysinfo.cpuinfo[cpu]
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, "implementation"
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, "RS2");
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break;
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case POWER_601:
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add_info( &sysinfo.cpuinfo[cpu]
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, "implementation"
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, "601");
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break;
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case POWER_603:
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add_info( &sysinfo.cpuinfo[cpu]
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, "implementation"
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, "603");
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break;
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case POWER_604:
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add_info( &sysinfo.cpuinfo[cpu]
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, "implementation"
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, "604");
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break;
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case POWER_620:
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add_info( &sysinfo.cpuinfo[cpu]
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, "implementation"
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, "620");
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break;
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case POWER_630:
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add_info( &sysinfo.cpuinfo[cpu]
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, "implementation"
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, "630");
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break;
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case POWER_A35:
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add_info( &sysinfo.cpuinfo[cpu]
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, "implementation"
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, "A35");
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break;
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case POWER_RS64II:
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add_info( &sysinfo.cpuinfo[cpu]
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, "implementation"
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, "RS64II");
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break;
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case POWER_RS64III:
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add_info( &sysinfo.cpuinfo[cpu]
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, "implementation"
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, "RS64III");
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break;
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}
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}
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else if (_system_configuration.architecture == IA64)
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{
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switch(_system_configuration.implementation)
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{
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case IA64_M1:
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add_info( &sysinfo.cpuinfo[cpu]
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, "implementation"
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, "IA64 M1");
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break;
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case IA64_M2:
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add_info( &sysinfo.cpuinfo[cpu]
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, "implementation"
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, "IA64 M2");
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break;
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}
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}
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sprintf(buf,"%d", _system_configuration.width);
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add_info( &sysinfo.cpuinfo[cpu], "width", buf);
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if (_system_configuration.cache_attrib & (1 << 31))
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{
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/* L1 cache is present */
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sprintf(buf,"%d", _system_configuration.icache_size);
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add_info( &sysinfo.cpuinfo[cpu], "L1 instruction cache size", buf);
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sprintf(buf,"%d", _system_configuration.dcache_size);
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add_info( &sysinfo.cpuinfo[cpu], "L1 data cache size", buf);
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}
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sprintf(buf,"%d", _system_configuration.L2_cache_size);
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add_info( &sysinfo.cpuinfo[cpu], "L2 cache size", buf);
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}
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sysinfo.flags = _glibtop_sysdeps_sysinfo;
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}
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glibtop_sysinfo *
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glibtop_get_sysinfo_s (glibtop *server)
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{
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static int first_time = 1;
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if (first_time)
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{
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init_sysinfo();
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first_time = 0;
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}
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return &sysinfo;
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}
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