Michael Brown
8406115834
Access to the gpxe.org and etherboot.org domains and associated resources has been revoked by the registrant of the domain. Work around this problem by renaming project from gPXE to iPXE, and updating URLs to match. Also update README, LOG and COPYRIGHTS to remove obsolete information. Signed-off-by: Michael Brown <mcb30@ipxe.org>
540 lines
14 KiB
C
540 lines
14 KiB
C
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/* epic100.c: A SMC 83c170 EPIC/100 fast ethernet driver for Etherboot */
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FILE_LICENCE ( GPL2_OR_LATER );
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/* 05/06/2003 timlegge Fixed relocation and implemented Multicast */
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#define LINUX_OUT_MACROS
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#include "etherboot.h"
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#include <ipxe/pci.h>
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#include <ipxe/ethernet.h>
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#include "nic.h"
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#include "console.h"
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#include "epic100.h"
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/* Condensed operations for readability */
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#define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
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#define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
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#define TX_RING_SIZE 2 /* use at least 2 buffers for TX */
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#define RX_RING_SIZE 2
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#define PKT_BUF_SZ 1536 /* Size of each temporary Tx/Rx buffer.*/
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/*
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#define DEBUG_RX
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#define DEBUG_TX
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#define DEBUG_EEPROM
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*/
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#define EPIC_DEBUG 0 /* debug level */
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/* The EPIC100 Rx and Tx buffer descriptors. */
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struct epic_rx_desc {
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unsigned long status;
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unsigned long bufaddr;
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unsigned long buflength;
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unsigned long next;
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};
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/* description of the tx descriptors control bits commonly used */
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#define TD_STDFLAGS TD_LASTDESC
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struct epic_tx_desc {
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unsigned long status;
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unsigned long bufaddr;
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unsigned long buflength;
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unsigned long next;
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};
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#define delay(nanosec) do { int _i = 3; while (--_i > 0) \
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{ __SLOW_DOWN_IO; }} while (0)
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static void epic100_open(void);
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static void epic100_init_ring(void);
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static void epic100_disable(struct nic *nic);
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static int epic100_poll(struct nic *nic, int retrieve);
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static void epic100_transmit(struct nic *nic, const char *destaddr,
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unsigned int type, unsigned int len, const char *data);
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#ifdef DEBUG_EEPROM
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static int read_eeprom(int location);
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#endif
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static int mii_read(int phy_id, int location);
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static void epic100_irq(struct nic *nic, irq_action_t action);
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static struct nic_operations epic100_operations;
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static int ioaddr;
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static int command;
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static int intstat;
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static int intmask;
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static int genctl ;
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static int eectl ;
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static int test ;
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static int mmctl ;
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static int mmdata ;
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static int lan0 ;
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static int mc0 ;
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static int rxcon ;
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static int txcon ;
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static int prcdar ;
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static int ptcdar ;
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static int eththr ;
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static unsigned int cur_rx, cur_tx; /* The next free ring entry */
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#ifdef DEBUG_EEPROM
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static unsigned short eeprom[64];
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#endif
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static signed char phys[4]; /* MII device addresses. */
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struct {
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struct epic_rx_desc rx_ring[RX_RING_SIZE]
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__attribute__ ((aligned(4)));
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struct epic_tx_desc tx_ring[TX_RING_SIZE]
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__attribute__ ((aligned(4)));
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unsigned char rx_packet[PKT_BUF_SZ * RX_RING_SIZE];
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unsigned char tx_packet[PKT_BUF_SZ * TX_RING_SIZE];
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} epic100_bufs __shared;
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#define rx_ring epic100_bufs.rx_ring
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#define tx_ring epic100_bufs.tx_ring
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#define rx_packet epic100_bufs.rx_packet
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#define tx_packet epic100_bufs.tx_packet
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/***********************************************************************/
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/* Externally visible functions */
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/***********************************************************************/
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static int
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epic100_probe ( struct nic *nic, struct pci_device *pci ) {
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int i;
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unsigned short* ap;
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unsigned int phy, phy_idx;
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if (pci->ioaddr == 0)
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return 0;
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/* Ideally we would detect all network cards in slot order. That would
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be best done a central PCI probe dispatch, which wouldn't work
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well with the current structure. So instead we detect just the
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Epic cards in slot order. */
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ioaddr = pci->ioaddr;
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nic->irqno = 0;
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nic->ioaddr = pci->ioaddr & ~3;
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/* compute all used static epic100 registers address */
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command = ioaddr + COMMAND; /* Control Register */
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intstat = ioaddr + INTSTAT; /* Interrupt Status */
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intmask = ioaddr + INTMASK; /* Interrupt Mask */
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genctl = ioaddr + GENCTL; /* General Control */
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eectl = ioaddr + EECTL; /* EEPROM Control */
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test = ioaddr + TEST; /* Test register (clocks) */
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mmctl = ioaddr + MMCTL; /* MII Management Interface Control */
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mmdata = ioaddr + MMDATA; /* MII Management Interface Data */
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lan0 = ioaddr + LAN0; /* MAC address. (0x40-0x48) */
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mc0 = ioaddr + MC0; /* Multicast Control */
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rxcon = ioaddr + RXCON; /* Receive Control */
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txcon = ioaddr + TXCON; /* Transmit Control */
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prcdar = ioaddr + PRCDAR; /* PCI Receive Current Descr Address */
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ptcdar = ioaddr + PTCDAR; /* PCI Transmit Current Descr Address */
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eththr = ioaddr + ETHTHR; /* Early Transmit Threshold */
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/* Reset the chip & bring it out of low-power mode. */
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outl(GC_SOFT_RESET, genctl);
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/* Disable ALL interrupts by setting the interrupt mask. */
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outl(INTR_DISABLE, intmask);
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/*
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* set the internal clocks:
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* Application Note 7.15 says:
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* In order to set the CLOCK TEST bit in the TEST register,
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* perform the following:
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*
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* Write 0x0008 to the test register at least sixteen
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* consecutive times.
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*
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* The CLOCK TEST bit is Write-Only. Writing it several times
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* consecutively insures a successful write to the bit...
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*/
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for (i = 0; i < 16; i++) {
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outl(0x00000008, test);
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}
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#ifdef DEBUG_EEPROM
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{
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unsigned short sum = 0;
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unsigned short value;
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for (i = 0; i < 64; i++) {
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value = read_eeprom(i);
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eeprom[i] = value;
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sum += value;
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}
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}
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#if (EPIC_DEBUG > 1)
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printf("EEPROM contents\n");
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for (i = 0; i < 64; i++) {
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printf(" %hhX%s", eeprom[i], i % 16 == 15 ? "\n" : "");
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}
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#endif
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#endif
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/* This could also be read from the EEPROM. */
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ap = (unsigned short*)nic->node_addr;
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for (i = 0; i < 3; i++)
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*ap++ = inw(lan0 + i*4);
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DBG ( " I/O %4.4x %s ", ioaddr, eth_ntoa ( nic->node_addr ) );
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/* Find the connected MII xcvrs. */
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for (phy = 0, phy_idx = 0; phy < 32 && phy_idx < sizeof(phys); phy++) {
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int mii_status = mii_read(phy, 0);
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if (mii_status != 0xffff && mii_status != 0x0000) {
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phys[phy_idx++] = phy;
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#if (EPIC_DEBUG > 1)
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printf("MII transceiver found at address %d.\n", phy);
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#endif
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}
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}
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if (phy_idx == 0) {
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#if (EPIC_DEBUG > 1)
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printf("***WARNING***: No MII transceiver found!\n");
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#endif
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/* Use the known PHY address of the EPII. */
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phys[0] = 3;
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}
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epic100_open();
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nic->nic_op = &epic100_operations;
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return 1;
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}
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static void set_rx_mode(void)
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{
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unsigned char mc_filter[8];
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int i;
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memset(mc_filter, 0xff, sizeof(mc_filter));
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outl(0x0C, rxcon);
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for(i = 0; i < 4; i++)
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outw(((unsigned short *)mc_filter)[i], mc0 + i*4);
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return;
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}
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static void
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epic100_open(void)
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{
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int mii_reg5;
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int full_duplex = 0;
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unsigned long tmp;
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epic100_init_ring();
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/* Pull the chip out of low-power mode, and set for PCI read multiple. */
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outl(GC_RX_FIFO_THR_64 | GC_MRC_READ_MULT | GC_ONE_COPY, genctl);
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outl(TX_FIFO_THRESH, eththr);
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tmp = TC_EARLY_TX_ENABLE | TX_SLOT_TIME;
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mii_reg5 = mii_read(phys[0], 5);
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if (mii_reg5 != 0xffff && (mii_reg5 & 0x0100)) {
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full_duplex = 1;
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printf(" full-duplex mode");
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tmp |= TC_LM_FULL_DPX;
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} else
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tmp |= TC_LM_NORMAL;
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outl(tmp, txcon);
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/* Give adress of RX and TX ring to the chip */
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outl(virt_to_le32desc(&rx_ring), prcdar);
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outl(virt_to_le32desc(&tx_ring), ptcdar);
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/* Start the chip's Rx process: receive unicast and broadcast */
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set_rx_mode();
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outl(CR_START_RX | CR_QUEUE_RX, command);
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putchar('\n');
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}
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/* Initialize the Rx and Tx rings. */
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static void
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epic100_init_ring(void)
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{
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int i;
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cur_rx = cur_tx = 0;
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for (i = 0; i < RX_RING_SIZE; i++) {
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rx_ring[i].status = cpu_to_le32(RRING_OWN); /* Owned by Epic chip */
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rx_ring[i].buflength = cpu_to_le32(PKT_BUF_SZ);
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rx_ring[i].bufaddr = virt_to_bus(&rx_packet[i * PKT_BUF_SZ]);
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rx_ring[i].next = virt_to_le32desc(&rx_ring[i + 1]) ;
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}
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/* Mark the last entry as wrapping the ring. */
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rx_ring[i-1].next = virt_to_le32desc(&rx_ring[0]);
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/*
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*The Tx buffer descriptor is filled in as needed,
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* but we do need to clear the ownership bit.
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*/
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for (i = 0; i < TX_RING_SIZE; i++) {
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tx_ring[i].status = 0x0000; /* Owned by CPU */
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tx_ring[i].buflength = 0x0000 | cpu_to_le32(TD_STDFLAGS << 16);
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tx_ring[i].bufaddr = virt_to_bus(&tx_packet[i * PKT_BUF_SZ]);
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tx_ring[i].next = virt_to_le32desc(&tx_ring[i + 1]);
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}
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tx_ring[i-1].next = virt_to_le32desc(&tx_ring[0]);
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}
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/* function: epic100_transmit
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* This transmits a packet.
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*
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* Arguments: char d[6]: destination ethernet address.
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* unsigned short t: ethernet protocol type.
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* unsigned short s: size of the data-part of the packet.
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* char *p: the data for the packet.
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* returns: void.
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*/
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static void
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epic100_transmit(struct nic *nic, const char *destaddr, unsigned int type,
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unsigned int len, const char *data)
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{
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unsigned short nstype;
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unsigned char *txp;
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int entry;
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unsigned long ct;
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/* Calculate the next Tx descriptor entry. */
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entry = cur_tx % TX_RING_SIZE;
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if ((tx_ring[entry].status & TRING_OWN) == TRING_OWN) {
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printf("eth_transmit: Unable to transmit. status=%4.4lx. Resetting...\n",
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tx_ring[entry].status);
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epic100_open();
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return;
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}
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txp = tx_packet + (entry * PKT_BUF_SZ);
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memcpy(txp, destaddr, ETH_ALEN);
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memcpy(txp + ETH_ALEN, nic->node_addr, ETH_ALEN);
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nstype = htons(type);
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memcpy(txp + 12, (char*)&nstype, 2);
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memcpy(txp + ETH_HLEN, data, len);
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len += ETH_HLEN;
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len &= 0x0FFF;
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while(len < ETH_ZLEN)
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txp[len++] = '\0';
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/*
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* Caution: the write order is important here,
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* set the base address with the "ownership"
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* bits last.
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*/
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tx_ring[entry].buflength |= cpu_to_le32(len);
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tx_ring[entry].status = cpu_to_le32(len << 16) |
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cpu_to_le32(TRING_OWN); /* Pass ownership to the chip. */
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cur_tx++;
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/* Trigger an immediate transmit demand. */
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outl(CR_QUEUE_TX, command);
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ct = currticks();
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/* timeout 10 ms for transmit */
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while ((le32_to_cpu(tx_ring[entry].status) & (TRING_OWN)) &&
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ct + 10*1000 < currticks())
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/* Wait */;
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if ((le32_to_cpu(tx_ring[entry].status) & TRING_OWN) != 0)
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printf("Oops, transmitter timeout, status=%4.4lX\n",
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tx_ring[entry].status);
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}
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/* function: epic100_poll / eth_poll
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* This receives a packet from the network.
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*
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* Arguments: none
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*
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* returns: 1 if a packet was received.
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* 0 if no pacet was received.
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* side effects:
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* returns the packet in the array nic->packet.
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* returns the length of the packet in nic->packetlen.
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*/
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static int
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epic100_poll(struct nic *nic, int retrieve)
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{
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int entry;
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int retcode;
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int status;
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entry = cur_rx % RX_RING_SIZE;
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if ((rx_ring[entry].status & cpu_to_le32(RRING_OWN)) == RRING_OWN)
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return (0);
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if ( ! retrieve ) return 1;
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status = le32_to_cpu(rx_ring[entry].status);
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/* We own the next entry, it's a new packet. Send it up. */
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#if (EPIC_DEBUG > 4)
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printf("epic_poll: entry %d status %hX\n", entry, status);
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#endif
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cur_rx++;
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if (status & 0x2000) {
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printf("epic_poll: Giant packet\n");
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retcode = 0;
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} else if (status & 0x0006) {
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/* Rx Frame errors are counted in hardware. */
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printf("epic_poll: Frame received with errors\n");
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retcode = 0;
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} else {
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/* Omit the four octet CRC from the length. */
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nic->packetlen = le32_to_cpu((rx_ring[entry].buflength))- 4;
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memcpy(nic->packet, &rx_packet[entry * PKT_BUF_SZ], nic->packetlen);
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retcode = 1;
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}
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/* Clear all error sources. */
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outl(status & INTR_CLEARERRS, intstat);
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/* Give the descriptor back to the chip */
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rx_ring[entry].status = RRING_OWN;
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/* Restart Receiver */
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outl(CR_START_RX | CR_QUEUE_RX, command);
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return retcode;
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}
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static void epic100_disable ( struct nic *nic __unused ) {
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/* Soft reset the chip. */
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outl(GC_SOFT_RESET, genctl);
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}
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static void epic100_irq(struct nic *nic __unused, irq_action_t action __unused)
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{
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switch ( action ) {
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case DISABLE :
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break;
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case ENABLE :
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break;
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case FORCE :
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break;
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}
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}
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#ifdef DEBUG_EEPROM
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/* Serial EEPROM section. */
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/* EEPROM_Ctrl bits. */
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#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
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#define EE_CS 0x02 /* EEPROM chip select. */
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#define EE_DATA_WRITE 0x08 /* EEPROM chip data in. */
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#define EE_WRITE_0 0x01
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#define EE_WRITE_1 0x09
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#define EE_DATA_READ 0x10 /* EEPROM chip data out. */
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#define EE_ENB (0x0001 | EE_CS)
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/* The EEPROM commands include the alway-set leading bit. */
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#define EE_WRITE_CMD (5 << 6)
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#define EE_READ_CMD (6 << 6)
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#define EE_ERASE_CMD (7 << 6)
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#define eeprom_delay(n) delay(n)
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static int
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read_eeprom(int location)
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{
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int i;
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int retval = 0;
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int read_cmd = location | EE_READ_CMD;
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outl(EE_ENB & ~EE_CS, eectl);
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outl(EE_ENB, eectl);
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/* Shift the read command bits out. */
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for (i = 10; i >= 0; i--) {
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short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
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outl(EE_ENB | dataval, eectl);
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eeprom_delay(100);
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outl(EE_ENB | dataval | EE_SHIFT_CLK, eectl);
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eeprom_delay(150);
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outl(EE_ENB | dataval, eectl); /* Finish EEPROM a clock tick. */
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eeprom_delay(250);
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}
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outl(EE_ENB, eectl);
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for (i = 16; i > 0; i--) {
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outl(EE_ENB | EE_SHIFT_CLK, eectl);
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eeprom_delay(100);
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retval = (retval << 1) | ((inl(eectl) & EE_DATA_READ) ? 1 : 0);
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outl(EE_ENB, eectl);
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eeprom_delay(100);
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}
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/* Terminate the EEPROM access. */
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outl(EE_ENB & ~EE_CS, eectl);
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return retval;
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}
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#endif
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#define MII_READOP 1
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#define MII_WRITEOP 2
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static int
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mii_read(int phy_id, int location)
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{
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int i;
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outl((phy_id << 9) | (location << 4) | MII_READOP, mmctl);
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/* Typical operation takes < 50 ticks. */
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for (i = 4000; i > 0; i--)
|
|
if ((inl(mmctl) & MII_READOP) == 0)
|
|
break;
|
|
return inw(mmdata);
|
|
}
|
|
|
|
static struct nic_operations epic100_operations = {
|
|
.connect = dummy_connect,
|
|
.poll = epic100_poll,
|
|
.transmit = epic100_transmit,
|
|
.irq = epic100_irq,
|
|
|
|
};
|
|
|
|
static struct pci_device_id epic100_nics[] = {
|
|
PCI_ROM(0x10b8, 0x0005, "epic100", "SMC EtherPowerII", 0), /* SMC 83c170 EPIC/100 */
|
|
PCI_ROM(0x10b8, 0x0006, "smc-83c175", "SMC EPIC/C 83c175", 0),
|
|
};
|
|
|
|
PCI_DRIVER ( epic100_driver, epic100_nics, PCI_NO_CLASS );
|
|
|
|
DRIVER ( "EPIC100", nic_driver, pci_driver, epic100_driver,
|
|
epic100_probe, epic100_disable );
|
|
|
|
/*
|
|
* Local variables:
|
|
* c-basic-offset: 8
|
|
* c-indent-level: 8
|
|
* tab-width: 8
|
|
* End:
|
|
*/
|