[riscv] Add support for reboot and power off via SBI

Signed-off-by: Michael Brown <mcb30@ipxe.org>

src/arch/riscv/include/bits/errfile.h

@@ -14,6 +14,8 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
  * @{
  */
 
+#define ERRFILE_sbi_reboot	( ERRFILE_ARCH | ERRFILE_CORE | 0x00000000 )
+
 /** @} */
 
 #endif /* _BITS_ERRFILE_H */

src/arch/riscv/include/bits/reboot.h

@@ -0,0 +1,14 @@
+#ifndef _BITS_REBOOT_H
+#define _BITS_REBOOT_H
+
+/** @file
+ *
+ * RISCV-specific reboot API implementations
+ *
+ */
+
+FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
+
+#include <ipxe/sbi_reboot.h>
+
+#endif /* _BITS_REBOOT_H */

src/arch/riscv/include/ipxe/sbi.h

@@ -148,6 +148,16 @@ sbi_ecall_3 ( int eid, int fid, unsigned long p0, unsigned long p1,
 	return ret;
 }
 
+/** Convert an SBI error code to an iPXE status code */
+#define ESBI( error ) EPLATFORM ( EINFO_EPLATFORM, error )
+
+/** System reset extension */
+#define SBI_SRST SBI_EID ( 'S', 'R', 'S', 'T' )
+#define SBI_SRST_SYSTEM_RESET 0x00	/**< Reset system */
+#define SBI_RESET_SHUTDOWN 0x00000000	/**< Shutdown */
+#define SBI_RESET_COLD 0x00000001	/**< Cold reboot */
+#define SBI_RESET_WARM 0x00000002	/**< Warm reboot */
+
 /** Debug console extension */
 #define SBI_DBCN SBI_EID ( 'D', 'B', 'C', 'N' )
 #define SBI_DBCN_WRITE 0x00		/**< Console Write */

src/arch/riscv/include/ipxe/sbi_reboot.h

@@ -0,0 +1,18 @@
+#ifndef _IPXE_BIOS_REBOOT_H
+#define _IPXE_BIOS_REBOOT_H
+
+/** @file
+ *
+ * Supervisor Binary Interface (SBI) reboot mechanism
+ *
+ */
+
+FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
+
+#ifdef REBOOT_SBI
+#define REBOOT_PREFIX_sbi
+#else
+#define REBOOT_PREFIX_sbi __sbi_
+#endif
+
+#endif /* _IPXE_BIOS_REBOOT_H */