954ba8a803
New TI SoCs from J7 and AM62 family have a camera pipeline that receives data using Cadence's DPHY-RX and CSI-RX bridge. A pixel-grabbing "shim" IP routes this incoming stream of data to the DMA subsystem, to finally store the frame data in memory. The driver for this is not merged in mainline yet, but v7 was posted [1] on linux-media list a few months ago. With some minor fixes, the work-in-progress v8 series [2] works with the simple pipeline handler, so we enable support for this device. Link: https://lore.kernel.org/all/20230314115516.667-1-vaishnav.a@ti.com/ [1] Link: https://github.com/jailuthra/linux/commits/6ff226ca13f34 [2] Signed-off-by: Jai Luthra <j-luthra@ti.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>